AS4C64M16D1A-6TIN
AS4C64M16D1A-6TCN
ꢀ
Pin Descriptions
Table 2. Pin Details
Symbol
CK,
Type
Description
are differential clock inputs. All address and control input
Input
Differential Clock: CK and
CK
CK
signals are sampled on the crossing of the positive edge of CK and negative edge of
.
CK
(both directions of the
Input and output data is referenced to the crossing of CK and
crossing)
CK
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes
low synchronously with clock, the internal clock is suspended from the next clock cycle and
the state of output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power Down and
Self Refresh modes.
BA0, BA1
A0-A13
Input
Input
Input
Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs: A0-A13 are sampled during the BankActivate command (row address A0-
A13) and Read/Write command (column address A0-A9 with A10 defining Auto Precharge).
Chip Select:
enables (sampled LOW) and disables (sampled HIGH) the command
CS
decoder. All commands are masked when
CS
is sampled HIGH.
provides for external
CS
CS
bank selection on systems with multiple banks. It is considered part of the command code.
Input
Row Address Strobe: The
signal defines the operation commands in conjunction
RAS
RAS
with the
and
signals and is latched at the positive edges of CK. When
and
WE
CAS
RAS
is asserted "HIGH," either the BankActivate command
are asserted "LOW" and
CS
CAS
or the Precharge command is selected by the
signal. When the
is asserted
WE
WE
"HIGH," the BankActivate command is selected and the bank designated by BA is turned
on to the active state. When the is asserted "LOW," the Precharge command is
WE
selected and the bank designated by BA is switched to the idle state after the precharge
operation.
Input
Input
Column Address Strobe: The
signal defines the operation commands in conjunction
CAS
CAS
signals and is latched at the positive edges of CK. When
with the
and
is
WE
is asserted "LOW," the column access is started by asserting
RAS
held "HIGH" and
RAS
CS
"LOW." Then, the Read or Write command is selected by asserting
CAS
"HIGH" or “LOW”.
WE
Write Enable: The
signal defines the operation commands in conjunction with the
WE
WE
signals and is latched at the positive edges of CK. The
CAS
and
input is used
WE
RAS
to select the BankActivate or Precharge command and Read or Write command.
LDQS,
UDQS
Input /
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe is
edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS
is for DQ0~7, UDQS is for DQ8~15.
LDM,
UDM
Input
Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle.
LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
DQ0 - DQ15
Input / Data I/O: The DQ0-DQ15 input and output data are synchronized with positive and
Output negative edges of LDQS and UDQS. The I/Os are byte-maskable during Writes.
VDD
Supply
±
Power Supply: 2.5V 0.2V .
VSS
VDDQ
VSSQ
VREF
NC
Supply Ground
Supply
±
DQ Power: 2.5V 0.2V . Provide isolated power to DQs for improved noise immunity.
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Supply Reference Voltage for Inputs: +0.5*VDDQ
-
No Connect: These pins should be left unconnected.
Confidential
- 5/62 -
Rev. 1.0 Oct.2015
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
