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The AS4C4M4F1Q is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) device that is organized as 4,194,304
words × 4 bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely
low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main
memory in PCs, workstations, routers and switch applications.
The device features a high speed page mode operation where read and write operations within a single row (or page) can be executed at very
high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling
edge of RAS and CAS inputs respectively. Four individual CAS pins allow for separate I/O operation which enables the device to operate in
parity mode. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to CAS assertion.
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with previous
valid data.
• CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
The AS4C4M4F1Q is available in the standard 28-pin plastic SOJ and 28-pin plastic TSOP packages. The AS4C4M4F1Q operates with a single
power supply of 5V 0.5V and provides TTL compatible inputs and outputs.
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Parameter
Symbol
VCC
Min
4.5
0.0
2.4
–0.5†
0
Nominal
Max
5.5
0.0
VCC
0.8
70
Unit
5.0
0.0
–
V
V
Supply voltage
Input voltage
GND
VIH
V
VIL
–
V
Ambient operating temperature
TA
°C
†
V
min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
IL
3/22/02; v.1.3
Alliance Semiconductor
P. 2 of 14
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
