AS4C4M32S
Figure 9. Read to Precharge
(CAS# Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Col A
Bank
Row
Bank(s)
ADDRESS
tRP
NOP
Precharge
READ A
NOP
NOP
NOP
NOP
NOP
Activate
COMMAND
CAS# latency=2
tCK2, DQ
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CAS# latency=3
tCK3, DQ
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Don’t Care
5
6
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BA = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the
read operation. Once this command is given, any subsequent command cannot occur within a time
delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BA = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
Figure 10. Burst Write Operation
(Burst Length = 4)
T3 T4 T5
T0
T1
T2
T6
T7
T8
CLK
NOP
WRITE A
DIN A0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQ
DIN A1
DIN A2
DIN A3
The first data element and the write
are registered on the same clock edge
Don’t Care
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
Figure 11. Write Interrupted by a Write
(Burst Length = 4)
Alliance Memory Confidential
9
Rev. 3.0 May. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
