AS4C4M16S
FEBRUARY 2011
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming
from Write command can occur on any clock cycle following the previous Write command (refer to the
following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A WRITE B
NOP
NOP
DIN B1
NOP
NOP
NOP
NOP
NOP
COMMAND
DQ
DIN A0
DIN B0
DIN B2
DIN B3
Figure 11. Write Interrupted by a Write (Burst Length = 4)
The Read command that interrupts a write burst without auto precharge function should be issued one
cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention,
input data must be removed from the DQs at least one clock cycle before the first read data appears on
the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be
ignored and writes will not be executed.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
DIN A0
NOP
READ
B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS# latency=2
tCK2, DQ
don’t care
don’t care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
CAS# latency=3
tCK3, DQ
don’t care
DIN A0
DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ
at least one clock cycle before the Read
data appears on the outputs to avoid data
contention
Figure 12. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without t he auto precharge function
should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals
tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data,
starting with the clock edge following the last data- in element and ending with the clock edge on which the
BankPrecharge/PrechargeAll command is entered (refer to the following figure).
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Rev2.0 May 2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
