AS4C4M16SA-C&I
Commands
1
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address)
The BankActivate command activates the idle bank designated by the BA0, 1 signal. By latching the row
address on A0 to A11 at the time of this command, the selected row access is initiated. The read or write
operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank activation. A
subsequent BankActivate command to a different row in the same bank can only be issued after the
previous active row has been precharged (refer to the following figure). The minimum time interval
between successive BankActivate commands to the same bank is defined by tRC(min.). The SDRAM has
four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore
it restricts the back-to-back activation of the two banks. tRRD(min.) specifies the minimum time required
between activating different banks. After this command is used, the Write command and the Block Write
command perform the no mask write operation.
T0
T1
T2
T3
Tn+3 Tn+4
Tn+5
Tn+6
CLK
Bank A
Bank A
Bank B
Bank A
ADDRESS
Row Addr.
Col Addr.
Row Addr.
Row Addr.
RAS# - CAS# delay(tRCD
)
RAS# - RAS# delay time(tRRD)
Bank A
Activate
Bank B
Activate
Bank A
Activate
R/W A with
AutoPrecharge
NOP
NOP
NOP
NOP
COMMAND
RAS# - Cycle time(tRC
)
AutoPrecharge
Begin
Don’t Care
Figure 3. BankActivate Command Cycle
(Burst Length = n)
2
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)
The BankPrecharge command precharges the bank designated by BA signal. The precharged bank is
switched from the active state to the idle state. This command can be asserted anytime after tRAS(min.) is
satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active
is specified by tRAS(max.). Therefore, the precharge function must be performed in any active bank within
tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be
activated again.
3
4
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0-A9 and A11 = Don't care)
The PrechargeAll command precharges all banks simultaneously and can be issued even if all banks are
not in the active state. All banks are then switched to the idle state.
Read command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least tRCD(min.) before the Read command is issued. During
read bursts, the valid data-out element from the starting column address will be available following the
CAS latency after the issue of the Read command. Each subsequent data-out element will be valid by the
next positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the
burst unless other command is initiated. The burst length, burst sequence, and CAS latency are
determined by the mode register, which is already programmed. A full-page burst will continue until
terminated (at the end of the page it will wrap to column 0 and continue.
Confidential
7
Rev.3.0
Mar./2015
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
