ꢀ
AS4C32M32MD1
ꢀ
Mode Register Set
The mode register stores the data for controlling the various operating modes of the mobile DDR, includes CAS latency, addressing
mode, burst length, test mode, and various vendor specific options. The default value of the mode register is not defined.
Therefore the mode register must be written after power up to operate the mobile DDR. The device should be activated with the
CKE already high prior to writing into the Mode Register. The Mode Register is written by using the MRS command. The state of the
address signals registered in the same cycle as MRS command is written in the mode register. The value can be changed as long as
all banks are in the idle state.
The mode register is divided into various fields depending on functionality. The burst length uses A2.. A0, CAS latency (read latency
from column address) uses A6.. A4. BA0 must be set to low for normal operation.
A9.. AꢀꢁꢂLVꢂreserved for future use.
BA1 selects Extended Mode Register Setup operation when set to 1. Refer to the table for specific codes for various burst length,
addressing modes and CAS latencies.
Mode Register Bitmap
$ꢀꢁꢃ$ꢀꢄꢅ$ꢆ3ꢇ
Address Bus
BA1
BA0
A9
0
A8
0
A7
0
A6
A5
A4
A3
BT
A2
A1
A0
0
0
CAS Latency
Burst Length
Mode Register
0
Register
Mode
Burst Type
A3
Access
BA1
Accessed Register
Type
0
1
Mode Register
0
1
Sequential
Interleaved
Extend. Mode Reg.
CAS Latency
A6
A5
A4
Latency
2
3
0
0
1
1
0
1
Burst Length
Length
A2
A1
A0
Sequential
Interleave
0
0
0
ꢀ
0
1
1
ꢁ
1
0
1
ꢁ
2
4
8
2
4
8
ꢀꢂ
ꢀꢂ
Confidential
-6-
Rev.1.0 Sep.2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
