AS4C32M16SM
Table 4: Pin and Ball Descriptions
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
CKE
Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides precharge power-down and SELF REFRESH
operation (all banks idle), active power-down (row active in any bank), or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous
except after the device enters power-down and self-refresh modes, where
CKE becomes asynchronous until after exiting the same mode. The input
buffers, including CLK, are disabled during power-down and self-refresh
modes, providing low stand by power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH,
but READ/WRITE bursts already in progress will continue, and DQM
operation will retain its DQ mask capability while CS# is HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
CS#
Input
CAS#, RAS#,WE#
Input
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
x16:DQML,
DQMHLDQM,
UDQM(54-ball)
Input/output mask: DQM is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQM is
sampled HIGH during a WRITE cycle. The output buffers are placed in a High-
Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle.
On the x4 and x8, DQML (pin 15) is a NC and DQMH is DQM. On the x16,
DQML corresponds to DQ[7:0], and DQMH corresponds to DQ[15:8]. DQML
and DQMH are considered same state when referenced as DQM.
Bank address input(s): BA[1:0] defines to which bank the ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Address inputs: A[12:0] are sampled during the ACTIVE command (row
address A[12:0]) and READ or WRITE command (column address A[9:0], A11,
and A12 for x4; A[9:0] and A11 for x8;A[9:0] for x16; with A10 defining auto
precharge) to select one location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command to determine if all
banks are to be precharged (A10 HIGH) or bank selected by A10 (LOW). The
address inputs also provide the op-code during a LOAD MODE REGISTER
command.
BA[1:0]
A[12:0]
Input
Input
x16:DQ[15:0]
I/O
Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 15, 42, 45, 48, and 51
are NC for x8; and pins 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NC
for x4).
VDDQ
VSSQ
VDD
VSS
Supply DQ power: DQ power to the die for improved noise immunity.
Supply DQ ground: DQ ground to the die for improved noise immunity.
Supply Power supply: +3.3V ±0.3V.
Supply Ground.
NC
-
These should be left unconnected.
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R e v 1 . 0 , J u l y 2 0 1 4
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
