AS4C32M16SB-6TIN
AS4C32M16SB-7TIN
AS4C32M16SB-7TCN
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
DIN A0
READ B
don’t care
don’t care
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS# Latency=2
tCK2, DQ
DOUT B0
DOUT B1
DOUT B0
DOUT B2
DOUT B1
DOUT B3
DOUT B2
CAS# Latency=3
tCK3, DQ
don’t care
DIN A0
DOUT B3
Input data must be removed from the DQ at
least one clock cycle before the Read data
appears on the outputs to avoid data contention
Figure 12. Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element is
registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals
must be used to mask input data, starting with the clock edge following the last data-in element and
ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the
following figure).
T0
T1
T2
T3
T4
T5
T6
T7
CLK
DQM
tRP
WRITE
NOP
NOP
Precharge
Bank (s)
NOP
NOP
Activate
NOP
COMMAND
ADDRESS
DQ
Bank
Col n
ROW
tWR
DIN
n
DIN
N+1
Don’t Care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Figure 13. Write to Precharge
7
Write and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A9 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in
this command and the auto precharge function is ignored.
Confidential
- 12/55 -
Rev.1.0 June 2016
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
