AS4C32M16SA
Version 2.0
512Mbit Single-Data-Rate (SDR)SDRAM
32Mx16 (8M x 16 x 4 Banks)
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power on and
initialization sequence guarantees the device is preconditioned to each user’s specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VCC and
VCCQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state.
The power on voltage must not exceed VCC+0.3V on any of the input pins or VCC supplies. The CLK signal must be
started at the same time. After power on, an initial pause of 200 ms is required followed by a precharge of both banks
using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM
and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also
required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to
unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A
Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a
burst cycle (interleaved or sequential), a CAS Latency Field to set the access time at clock cycle and a Operation mode
field to differentiate between normal operation (Burst read and burst Write) and a special Burst Read and Single Write
mode. The mode set operation must be done before any activate command after the initial power up. Any content of the
mode register can be altered by re-executing the mode set command. All banks must be in pre-charged state and CKE
must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP
command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set
operation. Address input data at this timing defines parameters to be set as shown in the previous table.
Read and Write Operation
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to
address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set.
A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, t
timing. WE is use d to define either a read (WE = H) or a write (WE = L) at this stage.
, from the RAS
RCD
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are
allowed at up to a 166 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set
operation, i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial data
accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a
burst length of 8 with interleave sequence; if the first ad-dress is ‘2’, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4,
and 5.
Full page burst operation is only possible using sequential burst type. Full Page burst operation does not terminate
once the burst length has been reached. (At the end of the page, it will wrap to the start address and continue.) In other
words, unlike burst length of 2, 4, and 8, full page burst continues until it is terminated using another command.
Alliance Memory Inc. reserves the rights to change the specifications and products without notice.
Alliance Memory, Inc., 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA
Tel: +1 650 610 6800 Fax: +1 650 620 9211
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ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
