AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Address Input for Mode Set (Mode Register Operation)
BA1 BA0 An~ A10 A9
Operation Mode
Address Bus (Ax)
Mode Register
A8 A7 A6 A5 A4 A3 A2 A1 A0
CAS Latency BT Burst Length
Burst Type
Operation Mode
A3
0
Type
BA1 BA0 An~A10 A9 A8 A7
Mode
Sequential
Interleave
Burst Read/Burst
Write
0
0
0
0
0
0
0
0
0
1
Burst Read/Single
Write
1
0
0
Burst Length
CAS Latency
Length
A6
0
A5
0
A4
0
Latency
Reserve
Reserve
2
A2
A1
A0
Sequential Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
0
0
1
0
1
0
4
4
0
1
1
3
8
8
1
0
0
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Full page
Reserve
Reserve
Reserve
Reserve
1
0
1
1
1
0
1
1
1
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum t or the refresh
RAS
interval time limits the number of random column accesses. A new burst access can be done even before the
previous burst ends. The interrupt operation at every clock cycles is supported. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. An
interrupt which accompanies with an operation change from a read to a write is possible by exploiting
DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and pre-charge operations on two or
more banks can realize fast serial data access modes among many different pages. Once two or more
banks are activated, column to column interleave operation can be done between different pages.
Confidential
- 8/48 -
Rev.1.0 June 2016
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
