AS4C32M16D1A-C&I
( BA0, BA1)
Table 10. MRS/EMRS
BA1
RFU
RFU
BA0
0
A12 ~ A0
MRS Cycle
1
Extended Functions (EMRS)
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength.
The default value of the extended mode register is not defined, therefore must be written after power up for proper
operation. The Extened Mode Register is written by asserting Low on CS
device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be
High). The state of A0 ~ A12, BA0 and BA1 is written in the mode register in the same cycle asCS
RAS CAS, and
RAS CAS
, , ,
WE , BA1 and BA0 (the
,
,
WE going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the
extended mode register. A1 is used for setting driver strength to normal, or weak. Two clock cycles are required to
complete the write operation in the extended mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used
for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific codes.
Table 11. Extended Mode Register Bitmap
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0
1
RFU must be set to “0”
DS1 RFU must be set to “0” DS0 DLL Extended Mode Register
BA0 Mode
A6 A1
Drive Strength
Comment
A0
0
DLL
0
0
1
1
0
1
MRS
0
1
0
1
Full
Weak
RFU
Enable
Disable
EMRS
1
Reserved For Future
Matched impedance Output driver matches impedance
6
Rev. 1.0
Mar. /2015
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
