AS4C2M32D1A-5BCN
AS4C2M32D1A-5BIN
Ball Descriptions
Table 3. Ball Details
Symbol
CK,
Type
Description
are differential clock inputs. All address and control input
Input
Differential Clock: CK and
CK
CK
signals are sampled on the crossing of the positive edge of CK and negative edge of
.
CK
(both directions of the
Input and output data is referenced to the crossing of CK and
crossing)
CK
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes
low synchronously with clock, the internal clock is suspended from the next clock cycle and
the state of output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power Down and
Self Refresh modes.
BA0, BA1
A0-A10
Input
Input
Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs: A0-A10 are sampled during the Bank Activate command (row address
A0-A10) and Read/Write command (column address A0-A7 with A10 defining Auto
Precharge) to select one location out of the 512K available in the respective bank. During a
Precharge command, A10 is sampled to determine if all banks are to be precharged (A10 =
HIGH). The address inputs also provide the op-code during a Mode Register Set or
Extended Mode Register Set command.
Input
Input
Chip Select:
enables (sampled LOW) and disables (sampled HIGH) the command
CS
CS
decoder. All commands are masked when
CS
bank selection on systems with multiple banks. It is considered part of the command code.
is sampled HIGH.
provides for external
CS
Row Address Strobe: The
signal defines the operation commands in conjunction
RAS
RAS
with the
and
signals and is latched at the positive edges of CK. When
and
WE
CAS
RAS
are asserted "LOW" and
is asserted "HIGH" either the BankActivate command or
CS
CAS
the Precharge command is selected by the
signal. When the
is asserted "HIGH"
WE
WE
the BankActivate command is selected and the bank designated by BA is turned on to the
active state. When the is asserted "LOW" the Precharge command is selected and the
WE
bank designated by BA is switched to the idle state after the precharge operation.
Input
Input
Column Address Strobe: The signal defines the operation commands in conjunction
CAS
CAS
signals and is latched at the positive edges of CK. When
with the
and
is
WE
is asserted "LOW" the column access is started by asserting
RAS
RAS
held "HIGH" and
CS
"LOW". Then, the Read or Write command is selected by asserting
CAS
"HIGH" or "LOW".
WE
Write Enable: The
signal defines the operation commands in conjunction with the
WE
WE
signals and is latched at the positive edges of CK. The
CAS
and
input is used
WE
RAS
to select the BankActivate or Precharge command and Read or Write command.
DQS0-DQS3 Input /
Output
Bidirectional Data Strobe: The DQSx signals are mapped to the following data bytes:
DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, DQS3 to DQ24-DQ31.
DM0 - DM3
Input
Data Input Mask: DM0-DM3 are byte specific. Input data is masked when DM is sampled
HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23-DQ16, DM1 masks
DQ15-DQ8, and DM0 masks DQ7-DQ0.
DQ0 - DQ31
Input / Data I/O: The DQ0-DQ31 input and output data are synchronized with positive and
Output negative edges of DQS0~DQS3. The I/Os are byte-maskable during Writes.
VDD
VSS
Supply
±
Power Supply: 2.5V 0.2V.
Supply Ground
VDDQ
Supply
±
DQ Power: 2.5V 0.2V . Provide isolated power to DQs for improved noise immunity.
Confidential
5 of 63
Rev.1.0 Dec 2015
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
