AS4C2M32D1A-5BCN
AS4C2M32D1A-5BIN
Table 11. MRS/EMRS
BA1
0
BA0
0
A10 ~ A0
MRS Cycle
0
1
Extended Functions (EMRS)
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power up for
proper operation. The Extended Mode Register is written by asserting Low on
,
,
,
WE , BA1 and BA0
CS RAS CAS
(the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE
should be High). The state of A0 ~ A10 and BA1 are written in the mode register in the same cycle as
,
CS
,
, and WE going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to
RAS CAS
writing into the extended mode register. A1 is used for setting driver strength. Two clock cycles are required to
complete the write operation in the extended mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used
for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific codes.
Table 12. Extended Mode Register Bitmap
BA1 BA0 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0
1
RFU must be set to “0”
DS
DLL Extended Mode Register
A0
0
DLL
BA0
0
Mode
A1
0
Drive Strength
Full
MRS
Enable
Disable
1
EMRS
1
RFU
1
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Rev.1.0 Dec 2015
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
