AS4C2M32D1A-5BCN
AS4C2M32D1A-5BIN
Table 17. Electrical Characteristics and Recommended A.C.Operating Condition
(VDD = 2.5V ± 0.2V, TA = -40~85 °C)
-5
Symbol
Parameter
Unit Note
Min.
Max.
12
CL = 2
CL = 2.5
CL = 3
7.5
ns
ns
ns
tCK
tCK
tCK
Clock cycle time
6
12
5
0.45
7.5
0.55
0.55
-
tCH
tCL
tHP
Clock high level width
Clock low level width
Clock half period
0.45
tCLMIN or tCHMIN
ns
ns
2
3
Data-out-high impedance time from CK,
Data-out-low impedance time from CK,
tHZ
-
0.7
0.7
0.6
0.7
CK
CK
tLZ
-0.7
-0.6
-0.7
ns
ns
ns
3
DQS-out access time from CK,
tDQSCK
tAC
CK
Output access time from CK,
CK
tDQSQ
tRPRE
tRPST
tDQSS
DQS-DQ Skew
Read preamble
Read postamble
CK to valid DQS-in
-
0.9
0.4
0.72
0
0.4
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tCK
ns
ns
ns
ns
ns
1.1
0.6
1.25
tWPRES DQS-in setup time
-
4
5
tWPRE
tWPST
tDQSH
tDQSL
tIS
DQS Write preamble
0.25
0.4
0.35
0.35
0.7
0.7
0.4
0.4
tHP - tQHS
55
-
DQS write postamble
0.6
DQS in high level pulse width
DQS in low level pulse width
Address and Control input setup time
Address and Control input hold time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ/DQS output hold time from DQS
Row cycle time
-
-
-
6
6
tIH
-
tDS
-
tDH
-
tQH
-
tRC
-
tRFC
tRAS
tRCD
tRP
Refresh row cycle time
70
-
Row active time
40
70K
Active to Read or Write delay
Row precharge time
15
-
15
-
tRRD
tWR
Row active to Row active delay
Write recovery time
10
-
15
-
tWTR
tMRD
tREFI
tXSRD
tXSNR
tDAL
tDIPW
tIPW
tQHS
tDSS
tDSH
Internal Write to Read Command Delay
Mode register set cycle time
Average Periodic Refresh interval
Self refresh exit to read command delay
10
-
10
-
-
15.6
7
200
75
-
Self refresh exit to non-read command delay
Auto Precharge write recovery + precharge time
DQ and DM input puls width
-
tWR+tRP
1.75
2.2
-
-
-
Control and Address input pulse width
Data Hold Skew Factor
-
0.5
-
DQS falling edge to CK setup time
DQS falling edge hold time from CK
0.2
0.2
-
Confidential
13 of 63
Rev.1.0 Dec 2015
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
