4Gb DDR3L -AS4C256M16D3L
Figure 3. State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and the
commands to control them. In particular, situations involving more than one bank, the enabling or disabling
of on-die termination and some other events are not captured in full detail
Power
applied
MRS,MPR,
Write
Leveling
Power
On
Reset
Procedure
Self
Refresh
Initialization
ZQCL
E
S
R
from any
state
S
MRS
Idle
X
RESET
R
ZQCL,ZQCS
ZQ
Calibration
REF
Refreshing
P
D
E
P
D
ACT
X
ACT = Active
PRE = Precharge
Active
Power
Down
Precharge
Power
Down
Activating
PREA = Precharge All
P
D
X
MRS = Mode Register Set
REF = Refresh
P
D
E
RESET = Start RESET Procedure
Bank
Activating
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
W
R
R
E
A
A
E
I
D
T
Write = WR, WRS4, WRS8
E
T
I
R
READ
WRITE
Write A = WRA, WRAS4, WRAS8
W
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
READ
A
Reading
Writing
WRITE A
Writing
WRITE
D
A
PDE = Enter Power-down
PDX = Exit Power-down
E
R
SRE = Self-Refresh entry
SRX = Self-Refresh exit
READ
A
MPR = Multi-Purpose Register
A
E
R
E
A
T
I
R
D
W
A
P
R
P
R
E
E
,
,
Reading
P
R
P
R
E
E
A
A
Automatic Sequence
Command Sequence
Precharging
Confidential
6
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
