4Gb DDR3L -AS4C256M16D3L
LDQS,
LDQS#
UDQS
UDQS#
LDM,
Input /
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe
is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM.
LDQS is for DQ0~7, UDQS is for DQ8~15. The data strobes LDOS and UDQS are paired
with LDQS# and UDQS# to provide differential pair signaling to the system during both
reads and writes.
Input
Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle.
LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
UDM
DQ0 - DQ15 Input /
Output
Data I/O: The data bus input and output data are synchronized with positive and negative
edges of DQS/DQS#. The I/Os are byte-maskable during Writes.
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to
the DDR3L SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS#. The ODT
pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT.
RESET#
Input
Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive
when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD
VDD
VSS
Supply
Supply
Supply
Supply
Power Supply: +1.35V -0.067V/+0.1V.
Ground
VDDQ
VSSQ
VREFCA
VREFDQ
ZQ
DQ Power: +1.35V -0.067V/+0.1V.
DQ Ground
Supply Reference voltage for CA
Supply Reference voltage for DQ
Supply Reference pin for ZQ calibration.
NC
-
No Connect: These pins should be left unconnected.
Confidential
8
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
