AS4C256M16D3B-12BCN
Basic Functionality
Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and continue for a burst
length of four or eight in a programmed sequence. Operation begins with the registration of an Active command, which
is then followed by a Read or Write command. The address bits registered coincident with the Active command are used
to select the bank and row to be accessed (BA0-BA2 select the bank; A0-A15 select the row).The address bits regis-
tered coincident with the Read or Write command are used to select the starting column location for the burst operation,
determine if the auto precharge command is to be issued (via A10/AP), and the select BC4 or BL8 mode “on the fly” (via
A12) if enabled in the mode register.
Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined manner. The following
sections provide detailed information covering device reset and initialization, register definition, command descriptions
and device operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain RESET below 0.2 x VDD (all other inputs may be undefined). RESET needs to
be maintained for minimum 200μs with stable power. CKE is pulled “Low” anytime before RESET being de-asserted
(min. time 10ns). The power voltage ramp time between 300mV to VDD min must be no longer than 200ms; and dur-
ing the ramp, VDD > VDDQ and VDD -VDDQ < 0.3 volts.
- VDD and VDDQ are driven from a single power converter output, AND
- The voltage levels on all pins other than VDD,VDDQ,VSS,VSSQ must be less than or equal to VDDQ and VDD on
one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V
max once power ramp is finished, AND
- Vref tracks VDDQ/2.
or
- Apply VDD without any slope reversal before or at the same time as VDDQ.
- Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
- The voltage levels on all pins other than VDD,VDDQ,VSS,VSSQ must be less than or equal to VDDQ and VDD on
one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET is de-asserted, wait for another 500us until CKE becomes active. During this time, the DRAM will start
internal initialization; this will bedone independently of external clocks.
3. Clocks (CK, CK) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active.
Since CKE is a synchronous signal, the corresponding setup time to clock (tIS) must be met. Also a NOP or Deselect
command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered “High”
after Reset, CKE needs to be continuously registered “High” until the initialization sequenceis finished, including expi-
ration of tDLLK and tZQinit.
4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET is asserted. Further, the
SDRAM keeps its on-die termination in high impedance state after RESET deassertion until CKE is registered HIGH.
The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered
HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1 and
the on-die termination is required to remain in the high impedance state, the ODT input signal must be statically held
LOW. In all cases, the ODT input signal remains static until the power up initialization sequence is finished, including
the expiration of tDLLK and tZQinit.
5. After CKE is registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command to
load mode register.(tXPR=Max(tXS, 5tCK)]
6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
BA0 and BA2, “High” to BA1.)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
BA2, “High” to BA0 and BA1.)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue ”DLL Enable” command,
provide “Low” to A0, ”High” to BA0 and “Low” to BA1-BA2)
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command, pro-
vide “High” to A8 and “Low” to BA0-2).
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQ init completed.
12. The DDR3 SDRAM is now ready for normal operation.
Confidential
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Rev.1.0 April 2016
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
