AS4C14400
®
Notes
1
2
3
ICC1, ICC3, ICC4, and ICC6 depend on cycle rate.
ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 16 ms).
4
AC Characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) ≥ GND and VIH
(max) ≤ VCC. See AC test conditions for more information.
5
6
VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by tCAC
.
7
Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the
specified tRAD (max) limit, then access time is controlled exclusively by tAA
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either tRCH or tRRH must be satisfied for a read cycle.
.
8
9
10 tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
11 tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWCS
≥
tWCS (min) and tWCH ≥ tWCH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle.
If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of tCAA or tCAC or tCAP
14 tASC ≥ tCP to achieve tPC (min) and tCAP (max) values.
15 These parameters are sampled and not 100% tested.
.
AC test conditions
- Access times are measured with output reference
+5V
levels of V = 2V and V = 0.8 V
OH
OL
- Input rise and fall times: 5 ns
R1 = 828W
D
out
+3.0V
90%
90%
10%
100 pF*
R2 = 295W
GND
*including scope
and jig capacitance
10%
Figure A: Input waveform
Figure B: Equivalent output load
Key to switching waveforms
Don’t care input
Rising input
Falling input
Undefined output
7
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
