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AS4C14405-50JC 参数 Datasheet PDF下载

AS4C14405-50JC图片预览
型号: AS4C14405-50JC
PDF下载: 下载PDF文件 查看货源
内容描述: 1M位× 4 CMOS DRAM(快速页面模式或EDO ) [1M-bit × 4 CMOS DRAM (Fast page mode or EDO)]
分类和应用: 动态存储器
文件页数/大小: 16 页 / 395 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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AS4C14400
®
Notes
1
2
3
I
CC1
, I
CC3
, I
CC4
, and I
CC6
depend on cycle rate.
I
CC1
and I
CC4
depend on output loading. Specified values are obtained with the output open.
An initial pause of 200
µs
is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 16 ms).
AC Characteristics assume t
T
= 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V
IL
(min)
GND and V
IH
(max)
V
CC
. See AC test conditions for more information.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
and V
IL
.
Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. t
RCD
(max) is specified as a reference point only. If t
RCD
is greater than the
specified t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. t
RAD
(max) is specified as a reference point only. If t
RAD
is greater than the
specified t
RAD
(max) limit, then access time is controlled exclusively by t
AA
.
Assumes three state test load (5 pF and a 380
Thevenin equivalent).
Either t
RCH
or t
RRH
must be satisfied for a read cycle.
t
OFF
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
t
WCS
, t
WCH
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t
WCS
t
WCS
(min) and t
WCH
t
WCH
(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle.
If t
RWD
t
RWD
(min), t
CWD
t
CWD
(min) and t
AWD
t
AWD
(min), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
Access time is determined by the longest of t
CAA
or t
CAC
or t
CAP
.
t
ASC
t
CP
to achieve t
PC
(min) and t
CAP
(max) values.
These parameters are sampled and not 100% tested.
4
5
6
7
8
9
10
11
12
13
14
15
AC test conditions
- Access times are measured with output reference
levels of V
OH
= 2V and V
OL
= 0.8 V
- Input rise and fall times: 5 ns
+3.0V
D
out
90%
10%
90%
10%
100 pF*
R2 = 295
W
*including scope
and jig capacitance
+5V
R1 = 828
W
Figure A: Input waveform
GND
Figure B: Equivalent output load
Key to switching waveforms
AAAAAA
Don’t care input
AAAAAA
AAAAAA
Rising input
AAAAAA
AAAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Falling input
AAAA
AAAA
AAAA
AAAA
AAAA
Undefined output
7