AS4C14400
®
Functional description
The AS4C14400 is a high performance CMOS Dynamic Random Access Memory organized as 1,048,576 words × 4 bits. The AS4C14400 is
fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power
and wide operating margins at component and system levels.
The AS4C14400 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the
1024
×
4 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease
the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column address strobe (CAS) which acts
as an output enable independent of RAS. Very fast CAS to output access time eases system design.
Refresh on the 1024 address combinations of A0 to A9 during a 16 ms period is accomplished by performing any of the following:
• RAS-only refresh cycles
• Hidden refresh cycles
• CAS-before-RAS refresh cycles
• Normal read or write cycles
The AS4C14400 is available in JEDEC standard 20/26-pin plastic SOJ and 20/26-pin plastic TSOP packages. System level features include
single power supply of 5.0
±
0.5V tolerance and direct interface with TTL logic families.
Logic block diagram
REFRESH
CONTROLLER
Vcc
GND
Column decoder
Sense amp
Data
I/O
I/O3
I/O2
I/O1
I/O0
RAS
RAS clock
generator
CAS
CAS clock
generator
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
OE
Address buffer
Row decoder
1024 × 1024 × 4
Array
(4,194,304)
WE
WE clock
generator
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Operating temperature
Symbol
V
CC
GND
V
IH
V
IL
TA
Minimum
4.5
0.0
2.4
–1.0
0
Nominal
5.0
0.0
–
–
Maximum
5.5
0.0
V
CC
+ 1
0.8
70
Unit
V
V
V
V
°C
Recommended operating conditions apply to all specifications unless otherwise noted.
2
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
