AS4C1M16F5
®
Notes
1
2
3
I
, I , and I
are dependent on frequency.
CC1 CC3
CC4
depend on output loading. Specified values are obtained with the output open.
I
and I
CC4
CC1
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended
periods of bias without clocks (greater than 8 ms).
4
AC Characteristics assume t = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V (min) ≥ GND and V (max)
T
IL
IH
≤ V
.
CC
5
6
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .
I
H
I
L
I
H
I
L
Operation within the t
RCD
ified t
(max) limit insures that t
(max) can be met. t
(max) is specified as a reference point only. If t
(max) is specified as a reference point only. If t
is greater than the spec-
is greater than the spec-
RAC
(max) limit, then access time is controlled exclusively by t
RCD
RAD
RCD
.
RCD
CAC
(max) can be met. t
7
Operation within the t
RAD
(max) limit insures that t
RAC
RAD
ified t
(max) limit, then access time is controlled exclusively by t .
RAD
AA
8
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either t or t must be satisfied for a read cycle.
9
RCH
RRH
10
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
is referenced from ris-
OFF
OFF
ing edge of RAS or CAS, whichever occurs last.
11
t
, t , t , t and t are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
WCS WCH RWD CWD
AWD
If tWS ≥ t (min) and tWH ≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle.
WS WH
If t
≥ t
RWD
(min), tCWD ≥ t
(min) and tAWD ≥ t
(min), the cycle is a read-write cycle and the data out will contain data read from the selected
RWD
CWD
AWD
cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t or t or t
CAA CAC
CPA
14
tASC ≥ t to achieve t (min) and t (max) values.
CP PC CPA
15 These parameters are sampled and not 100% tested.
16 These characteristics apply to AS4C1M16F5 5V devices.
AC test conditions
- Access times are measured with output reference levels
of VOH = 2.4V and VOL = 0.4V,
+5V
V
IH = 2.4V and VIL = 0.8V
R1 = 828Ω
- Input rise and fall times: 2 ns
D
out
100 pF*
R2 = 295Ω
*including scope
and jig capacitance
GND
Figure A: Equivalent output load
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
3/22/02; v.0.9.2
Alliance Semiconductor
P. 8 of 22
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
