AS4C16M32MD1
2.3 Pin Description
CK, CK# (input pins)
Clock: The CK and the CK# are the differential clock inputs. All address and control input signals are
samples on the crossing of the positive edge of CK and negative edge of CK. Input and output data
is referenced to the cross of CK and CK# (both directions of crossing). Internal signals are derived
from CK/CK#.
CKE (Input pins)
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input
buffers and output drivers. Taking CKE LOW provides PRE-CHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is
synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously.
Input buffers, excluding CK, CK# and CKE are disabled during power-down and self-refresh mode
which are contrived for low standby power consumption.
CS# (input pin)
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All
commands are masked when CS# is registered HIGH. CS# provides for external bank selection on
systems with multiple banks. CS# is considered part of the command code.
RAS#, CAS#, and WE# (input pins)
Command Inputs: These pins define operating commands (read, write, etc.) depending on the
combinations of their voltage levels. See "Command operation".
LDM, UDM (input pins) for x32 DM0-DM3
Input Data Mask: Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input-only, the DM loading matches the DQ and DQS loading.
For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1
corresponds to the data on DQ8-DQ15, DM2 corresponds to the data on
DQ16-DQ23, and DM3 corresponds to the data on DQ24-DQ31.
BA0, BA1 (input pins)
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE
command is being applied.
A0 [n:0] (input pins)
Address Inputs: provide the row address for ACTIVE commands, and the column address and AUTO
PRECHARGE bit for READ / WRITE commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the op-code during a MODE REGISTER SET command.
Confidential
5
Rev. 1.0/July 2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
