AS4C16M32MD1
5.2 Register Definition
5.2.1 Mode Register
The Mode Register is used to define the specific mode of operation of the LPDDR SDRAM. This
definition includes the definition of a burst length, a burst type, a CAS latency as shown below
table.
The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and
BA1=0) and will retain the stored information until it is reprogrammed, the device goes into Deep
Power-Down mode, or the device loses power.
Mode Register bits A0-A2 specify the burst length, A3 the type of burst (sequential or interleave),
A4-A6 the CAS latency. A logic 0 should be programmed to all the undefined addresses bits to
ensure future compatibility.
The Mode Register must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent operation. Violating
either of these requirements will result in unspecified operation. Reserved states should not be
used, as unknown operation or incompatibility with future versions may result.
5.2.1.1 Burst Length
Read and write accesses to the LPDDR SDRAM are burst oriented, with the burst length being set as
in Table 3, and the burst order as in Table 4.
The burst length determines the maximum number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types. A burst length of 16 is optional and some vendors may
choose to implement it.
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Rev. 1.0/July 2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
