AS4C16M16SA
Figure 37. Full Page Write Cycle
(Burst Length=Full Page)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBy
RBy
RAx
RBx
RBx
A0-A9,
RAx
CAx
CBx
A11-A12
DQM
DQ
Data is ignored
Hi-Z
DAx
DAx+1 DAx+2 DAx+3 DAx-1
Activate
DAx
DAx+1
DBx
DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
Full Page burst operation does not
Don’t Care
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Confidential
46
Rev. 2.0 63nm Mar /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
