AS4C16M16SA
Figure 30. Random Row Write (Interleaving Banks)
(Burst Length=8)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBx
RBx
RAy
RAy
A0-A9,
RAx
CAx
CBx
CAy
A11-A12
tRCD
tWR*
tRP
tWR*
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Activate
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Don’t Care
*tWR>tWR (min.)
Confidential
35
Rev. 2.0 63nm Mar /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
