AS4C16M16SA
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
Bank A
Activate
Bank A
Activate
WRITE A
Auto Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tDAL
DIN A0
DIN A1
DQ
tDAL=tWR+tRP
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
Figure 14. Burst Write with Auto-Precharge
(Burst Length = 2)
8
Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A12 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The Mode
Register Set command programs the values of CAS latency, Addressing Mode and Burst Length in the
Mode register to make SDRAM useful for a variety of different applications. The default values of the Mode
Register after power-up are undefined; therefore this command must be issued at the power-up sequence.
The state of pins A0~ A12 in the same cycle is the data written to the mode register. Two clock cycles are
required to complete the write in the mode register (refer to the following figure). The contents of the mode
register can be changed using the same command and the clock cycle requirements during operation as
long as all banks are in the idle state.
Table 5. Mode Register Bitmap
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
RFU* RFU* WBL Test Mode
0
CAS Latency
Burst Length
A9 Write Burst Mode
A8 A7
Test Mode
Normal
Vendor Use Only
Vendor Use Only
A3
0
1
Burst Type
Sequential
Interleave
0
1
Burst
Single Bit
0
1
0
0
0
1
A6
0
0
0
0
A5
A4
0
1
0
1
CAS Latency
Reserved
Reserved
2 clocks
3 clocks
Reserved
A2
0
0
0
0
A1
0
0
1
1
A0
0
1
0
1
Burst Length
0
0
1
1
0
1
2
4
8
1
0
1
1
1
Full Page (Sequential)
All other Reserved
All other Reserved
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
Confidential
12
Rev. 2.0 63nm Mar /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
