1Gb DDR3L – AS4C128M8D3L
Figure 72. Asynchronous ODT Timings on DDR3L SDRAM with fast ODT transition
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK
CKE
tIS
tIH
tIS
tIH
ODT
RTT
tAONPD
(min)
tAOFPD
(min)
RTT
tAONPD
(max)
tAOFPD
(max)
TRANSITIONING DATA
Don't Care
Figure 73. Synchronous to asynchronous transition during Precharge Power Down
(with DLL frozen) entry (AL = 0; CWL = 5; tANPD = WL - 1 = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
Ta0
Ta1
Ta2
Ta3
CK#
CK
NOP
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CKE
tRFC (min)
tANPD
PD entry transition period
tCPDED(min)
Last sync.
ODT
tAOF
(min)
RTT
RTT
ODTLoff
tAOFPD
(max)
tAOF
(max)
ODTLoff + tAOFPD
(min)
Sync. or
async. ODT
tAOFPD
(min)
RTT
RTT
ODTLoff + tAOFPD
(max)
First async.
ODT
tAOFPD
(min)
RTT
RTT
tAOFPD
(max)
TIME BREAK
TRANSITIONING DATA
Don't Care
Figure 74. Synchronous to asynchronous transition after Refresh command
(AL = 0; CWL = 5; tANPD = WL - 1 = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
Ta0
Ta1
Ta2
Ta3
CK#
CK
NOP
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CKE
tRFC (min)
tANPD
PD entry transition period
tCPDED(min)
Last sync.
ODT
tAOF
(min)
RTT
RTT
ODTLoff
tAOFPD
(max)
tAOF
(max)
ODTLoff + tAOFPD
(min)
Sync. or
async. ODT
tAOFPD
(min)
RTT
RTT
ODTLoff + tAOFPD
(max)
First async.
ODT
tAOFPD
(min)
RTT
RTT
tAOFPD
(max)
TIME BREAK
TRANSITIONING DATA
Don't Care
Confidential
85
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
