1Gb DDR3L – AS4C128M8D3L
On-Die Termination (ODT)
On-die termination (ODT) is a feature that enables the DRAM to enable/disable and turn on/off termination
resistance for each DQ, DQS, DQS#, and DM for the x8 configurations (and TDQS, TDQS# for the x8 configuration,
when enabled).
ODT is designed to improve signal integrity of the memory channel by enabling the DRAM controller to
independently turn on/off the DRAM’s internal termination resistance for any grouping of DRAM devices. ODT is
not supported during DLL disable mode (simple functional representation shown below). The switch is enabled by
the internal ODT control logic, which uses the external ODT ball and other control information.
Figure 21. Functional representation of ODT
ODT
VDDQ / 2
RTT
To other circuitry
like RCV,...
Switch
DQ, DQS,
DM, TDQS
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control
information. The value of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if the
Mode Register MR1 and MR2 are programmed to disable ODT and in self-refresh mode.
ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if either of MR1 {A2, A6, A9} or MR2 {A9, A10} are non-zero. In this case, the value of
RTT is determined by the settings of those bits.
Application: Controller sends WR command together with ODT asserted.
One possible application: The rank that is being written to provides termination.
DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR)
DRAM does not use any write or read command decode information.
Table 25. Termination Truth Table
ODT pin
DRAM Termination State
0
1
OFF
On, (Off, if disabled by MR1 (A2, A6, A9) and MR2 (A9, A10) in general)
Confidential
51
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
