1Gb DDR3L – AS4C128M8D3L
Figure14. Timing details of Write Leveling sequence
(DQS – DQS# is capturing CK – CK# low at T1 and CK – CK# high at T2)
T2
T1
tWLH
Notes 5
tWLS
tWLS
tWLH
CK#
CK
Notes 1
Notes 2
MRS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tMOD
ODT
Notes 6
Notes 6
Notes 6
Notes 6
tDQSH
tDQSH
tDQSL
tDQSL
Notes 4
tWLDQSEN
Diff_DQS
tWLMRD
tWLO
One Prime DQ:
Notes 3
tWLO
Prime DQ
tWLO
Late Remaining DQs
Early Remaining DQs
tWLO
tWLOE
All DQs are Prime:
Notes 3
tWLO
Late Prime DQs
tWLOE
tWLMRD
tWLO
Notes 3
tWLO
Early Prime DQs
tWLO
tWLOE
NOTES
1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or Deselect.
UNDEFINED Driving MODE TIME BREAK
Don't Care
3. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low, as shown in above Figure,
and maintained at this state through out the leveling procedure.
4. diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown with dotted line.
5. CK, CK# : CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent.
Confidential
41
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
