1Gb DDR3L – AS4C128M8D3L
Figure 12. Change Frequency during Precharge Power-down
PREVIOUS CLOCK FREQUENCY
NEW CLOCK FREQUENCY
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Td1
Te0
Te1
CK#
CK
tCHb tCLb
tCKb
tCHb tCLb
tCKb
tCH
tCL
tCHb tCLb
tCKb
tCKSRE
tCK
tCKSRX
tCKE
tIH
tIS
tIH
CKE
tIS
tCPDED
NOP
NOP
NOP
NOP
NOP
MRS
NOP
VALID
VALID
COMMAND
ADDRESS
DLL
RESET
tXP
tIH
tAOFPD / tAOF
ODT
tIS
DQS#
DQS
High-Z
High-z
DQ
DM
tDLLK
Enter PRECHARGE
Power-Down Mode
Exit PRECHARGE
Power-Down Mode
Frequency Change
Indicates a break
in time scale
NOTES
1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down.
Don't Care
2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1;refer to ODT timing section for exact requirements
3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state, as shown in Figure 13. If the RTT_NOM feature was disabled in the mode
register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case.
Confidential
38
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
