1Gb DDR3L – AS4C128M8D3L
- DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon
returning to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0=0), the
DLL is automatically disabled when entering Self-Refresh operation and is automatically re-enable upon exit of Self-
Refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a
Read or synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the
external clock. Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON, or tAOF
parameters. During tDLLK, CKE must continuously be registered high. DDR3L SDRAM does not require DLL for any
Write operation, expect when RTT_WR is enabled and the DLL is required for proper ODT operation. For more
detailed information on DLL Disable operation are described in DLL-off Mode. The direct ODT feature is not
supported during DLL-off mode. The on-die termination resistors must be disabled by continuously registering the
ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register set command
during DLL-off mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2
{A10, A9} = {0, 0}, to disable Dynamic ODT externally
- Output Driver Impedance Control
The output driver impedance of the DDR3L SDRAM device is selected by MR1 (bit A1 and A5) as shown in MR1
definition figure.
- ODT Rtt Values
DDR3L SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal
termination value Rtt_Nom is programmable in MR1. A separate value (Rtt_WR) may be programmable in MR2 to
enable a unique Rtt value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even
when Rtt_Nom is disabled.
- Additive Latency (AL)
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidth in
DDR3L SDRAM. In this operation, the DDR3L SDRAM allows a read or write command (either with or without auto-
precharge) to be issued immediately after the active command. The command is held for the time of the Additive
Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and
CAS Latency (CL) register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency
(CWL) register settings. A summary of the AL register options are shown in MR.
- Write leveling
For better signal integrity, DDR3L memory module adopted fly-by topology for the commands, addresses, control
signals, and clocks. The fly-by topology has benefits from reducing number of stubs and their length but in other
aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes difficult for the
Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the controller should support ‘write leveling’
in DDR3L SDRAM to compensate for skew.
- Output Disable
The DDR3L SDRAM outputs maybe enable/disabled by MR1 (bit 12) as shown in MR1 definition. When this feature
is enabled (A12=1) all output pins (DQs, DQS, DQS#, etc.) are disconnected from the device removing any loading
of the output drivers. This feature may be useful when measuring modules power for example. For normal operation
A12 should be set to ‘0’.
- TDQS enable
TDQS (Termination Data Strobe) is a feature of DDR3L SDRAM that provides additional termination resistance
outputs that may be useful in some system configurations. In contrast to the RDQS function of DDR2 SDRAM,
TDQS provides the termination resistance function only. The data strobe function of RDQS is not provided by TDQS.
The TDQS and DM functions share the same pin. When the TDQS function is enabled via the mode register, the
DM function is not supported. When the TDQS function is disabled, the DM function is provided and the TDQS# pin
is not used. The TDQS function is available in X8 DDR3L SDRAM only
Confidential
17
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
