AS4C128M32MD2A-18BIN
AS4C128M32MD2A-25BIN
Functional Description
Mobile LPDDR2 is a high-speed SDRAM internally configured as a 8-bank memory device. LPDDR2 devices use a double
data rate architecture on the command/address (CA) bus to reduce the number of input pins in the system.
The 10-bit CA bus is used to transmit command, address, and bank information. Each command uses one clock cycle,
during which command information is transferred on both the rising and falling edges of the clock.
LPDDR2 devices use a double data rate architecture on the DQ pins to achieve high-speed operation. The double data rate
architecture is essentially a 4n pre-fetch architecture with an interface designed to transfer two data bits per DQ every clock
cycle at the I/O pins. A single read or WRITE access for the LPDDR2 effectively consists of a single 4n-bit-wide, one-clock-
cycle data transfer at the internal SDRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the
I/O pins.
Read and write accesses are burst oriented; accesses start at a selected location and continue for a programmed number of
locations in a programmed sequence.
Accesses begin with the registration of an ACTIVATE command followed by a READ or WRITE command. The address and
BA bits registered coincident with the ACTIVATE command are used to select the row and bank to be accessed.
The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting
column location for the burst access.
Confidential
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Rev.1.0 Dec. 2017
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
