2Gb DDR3L – AS4C128M16D3L
Reset Procedure at Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET
needs to be maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time
10ns).
2. Follow Power-up Initialization Sequence step 2 to 11.
3. The Reset sequence is now completed. DDR3L SDRAM is ready for normal operation.
Figure 5. Reset Procedure at Power Stable Condition
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK#
CK
tCKSRX
VDD
VDDQ
T=100ns
T=500μs
RESET#
CKE
tIS
Tmin=10ns
tDLLK
tIS
tXPR
tMRD
tMRD
tMRD
tMOD
tZQinit
Note 1
MRS
MR2
MRS
MR3
MRS
MR1
MRS
MR0
ZQCL
Note 1
VALID
VALID
COMMAND
BA
tIS
tIS
VALID
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
ODT
RTT
NOTE 1. From time point “Td”until “Tk”NOP or DES commands must be applied between MRS and ZQCL commands.
TIME BREAK
Don't Care
Confidential
11
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
