2Gb DDR3L – AS4C128M16D3L
Figure 75. Asynchronous to synchronous transition during Precharge Power Down
(with DLL frozen) exit (CL = 6; AL = CL - 1; CWL = 5; tANPD = WL - 1 = 9)
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Td0
Td1
CK#
CK
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CKE
tXPDLL
tANPD
PD exit transition period
Last async.
ODT
tAOFPD
(min)
RTT
RTT
tAOFPD
(max)
ODTLoff + tAOF
(min)
tAOFPD
(max)
Sync. or
async. ODT
tAOFPD
(min)
RTT
RTT
ODTLoff + tAOF
(max)
ODTLoff
First sync.
ODT
tAOF
(min)
RTT
RTT
tAOF
(max)
TIME BREAK
TRANSITIONING DATA
Don't Care
Figure 76. Transition period for short CKE cycles, entry and exit period overlapping
(AL = 0, WL = 5, tANPD = WL - 1 = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK#
CK
NOP
NOP
NOP
NOP
COMMAND
CKE
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tANPD
tRFC (min)
PD entry transition period
PD exit transition period
tANPD
tXPDLL
short CKE low transition period
CKE
tANPD
short CKE high transition period
tXPDLL
Don't Care
TIME BREAK
Confidential
82
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
