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AS4C128M16D3L-12BCN 参数 Datasheet PDF下载

AS4C128M16D3L-12BCN图片预览
型号: AS4C128M16D3L-12BCN
PDF下载: 下载PDF文件 查看货源
内容描述: [Fully synchronous operation]
分类和应用:
文件页数/大小: 84 页 / 2090 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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2Gb DDR3L AS4C128M16D3L  
Reference Load for AC Timing and Output Slew Rate  
The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing  
parameters of the device as well as output slew rate measurements.  
It is not intended as a precise representation of any particular system environment or a depiction of the actual load  
presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing  
reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or  
more coaxial transmission lines terminated at the tester electronics.  
Figure 24. Reference Load for AC Timing and Output Slew Rate  
VDDQ  
DUT  
DQ  
25 Ohm  
CK, CK#  
DQS  
VTT = VDDQ/2  
DQS#  
Table 38. AC Overshoot/Undershoot Specification for Address and Control Pins  
Parameter  
-12  
0.4  
Unit  
Maximum peak amplitude allowed for overshoot area.  
Maximum peak amplitude allowed for undershoot area.  
Maximum overshoot area above VDD  
V
0.4  
V
0.33  
0.33  
V-ns  
V-ns  
Maximum undershoot area below VSS  
Table 39. AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask  
Parameter  
-12  
0.4  
Unit  
Maximum peak amplitude allowed for overshoot area.  
Maximum peak amplitude allowed for undershoot area.  
Maximum overshoot area above VDD  
V
0.4  
V
V-ns  
V-ns  
0.13  
0.13  
Maximum undershoot area below VSS  
Confidential  
57  
Rev. 2.0  
Aug. /2014  
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