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AS4C128M16D3L-12BCN 参数 Datasheet PDF下载

AS4C128M16D3L-12BCN图片预览
型号: AS4C128M16D3L-12BCN
PDF下载: 下载PDF文件 查看货源
内容描述: [Fully synchronous operation]
分类和应用:
文件页数/大小: 84 页 / 2090 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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2Gb DDR3L AS4C128M16D3L  
128M x 16 bit DDR3L Synchronous DRAM (SDRAM)  
Confidential  
Features  
Advanced (Rev. 2.0, Aug. /2014)  
Overview  
JEDEC Standard Compliant  
The 2Gb Double-Data-Rate-3 (DDR3L) DRAMs is  
double data rate architecture to achieve high-speed  
operation. It is internally configured as an eight bank  
DRAM.  
The 2Gb chip is organized as 16Mbit x 16 I/Os x 8  
bank devices. These synchronous devices achieve high  
speed double-data-rate transfer rates of up to 1600  
Mb/sec/pin for general applications.  
The chip is designed to comply with all key DDR3L  
DRAM key features and all of the control and address  
inputs are synchronized with a pair of externally  
supplied differential clocks. Inputs are latched at the  
cross point of differential clocks (CK rising and CK#  
falling). All I/Os are synchronized with differential DQS  
pair in a source synchronous fashion.  
These devices operate with a single 1.35V -0.067V  
/+0.1V power supply and are available in BGA  
packages.  
Power supplies: VDD & VDDQ = 1.35V  
Backward compatible to VDD & VDDQ = 1.5V ±0.075V  
Operating temperature:  
- Commercial (0 ~ 95°C)  
- Industrial (-40 ~ 95°C)  
Supports JEDEC clock jitter specification  
Fully synchronous operation  
Fast clock rate: 800MHz  
Differential Clock, CK & CK#  
Bidirectional differential data strobe  
- DQS & DQS#  
8 internal banks for concurrent operation  
8n-bit prefetch architecture  
Internal pipeline architecture  
Precharge & active power down  
Programmable Mode & Extended Mode registers  
Additive Latency (AL): 0, CL-1, CL-2  
Programmable Burst lengths: 4, 8  
Burst type: Sequential / Interleave  
Output Driver Impedance Control  
8192 refresh cycles / 64ms  
- Average refresh period  
℃ ≦  
7.8μs @ -40  
TC +85  
℃ <  
3.9μs @ +85  
≦ ℃  
TC +95  
Write Leveling  
OCD Calibration  
Dynamic ODT (Rtt_Nom & Rtt_WR)  
RoHS compliant  
Auto Refresh and Self Refresh  
96-ball 9 x 13 x 1.2mm FBGA package  
- Pb and Halogen Free  
Table 1. Speed Grade Information  
Speed Grade  
Clock Frequency  
CAS Latency  
tRCD  
tRP  
(ns)  
(ns)  
DDR3L-1600  
800 MHz  
11  
13.75  
13.75  
Table 2. Ordering Information  
Product part No Org  
Temperature  
Package  
AS4C128M16D3L-12BCN 128M x 16  
Commercial (Extended)  
0°C to 95°C  
Industrial  
96-ball FBGA  
96-ball FBGA  
AS4C128M16D3L-12BIN  
128M x 16  
-40°C to 95°C (Extended)  
Confidential  
2
Rev. 2.0  
Aug. /2014