AS4C128M16D3A-12BIN
Figure 70. Dynamic ODT: Behavior with ODT pin being asserted together with write
command for a duration of 6 clock cycles, example for BC4
(via MRS or OTF), AL = 0, CWL = 5.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
NOP
NOP
WRS4
VALID
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
ODTLcnw
ODTH4
ODTLon
ODTLoff
ODT
RTT
tAOF
tAON
tADC
(min)
(min)
(min)
RTT_WR
RTT_NOM
tAOF
tADC
(max)
tADC
(max)
(max)
ODTLcwn4
DQS, DQS#
DQ
WL
Din
n
Din
n+1
Din
n+2
Din
n+3
NOTES:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied. TRANSITIONING DON T CARE
2. ODT registered low at T5 would also be legal.
TRANSITIONING DATA
Don't Care
Figure 71. Dynamic ODT: Behavior with ODT pin being asserted together with write
command for a duration of 4 clock cycles
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
NOP
NOP
WRS4
VALID
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
ODTLcnw
ODTH4
ODTLon
ODTLoff
ODT
RTT
tAON
tAOF
(min)
(min)
RTT_WR
tAOF
tADC
(max)
(max)
ODTLcwn4
WL
DQS, DQS#
DQ
Din
n
Din
n+1
Din
n+2
Din
n+3
NOTES:
Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH4 = 4 is exactly satisfied.
TRANSITIONING DATA
Don't Care
Confidential
-79／83-
Rev. 1.0 May 2016
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
