AS4C128M16D3A-12BIN
- Data Setup, Hold, and Slew Rate De-rating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet
tDS(base) and tDH(base) value to the ΔtDS and ΔtDH derating value respectively.
Example: tDS (total setup time) = tDS(base) + ΔtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc)
and the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate
between the last crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than
the nominal slew rate line between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the
actual signal is later than the nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate
of the tangent line to the actual signal from the ac level to dc level is used for derating value. Hold (tDH) nominal
slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of Vref(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew
rate line between shaded ‘dc level to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is
earlier than the nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent
line to the actual signal from the dc level to Vref(dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached
VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and
reach VIH/IL(ac).
For slew rates in between the values listed in the following tables, the derating values may be obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Table 42. Data Setup and Hold Base
-12
10
-
Symbol
Reference
Unit Note
VIH/L(ac)
VIH/L(ac)
VIH/L(dc)
tDS(base) AC150
tDS(base) AC135
tDH(base) DC100
tDH(base) DC100
ps
ps
ps
ps
2
1
1
2
45
45
VIH/L(dc)
NOTE 1: (ac/dc referenced for 2 V/ns Address/Command slew rate and 4 V/ns differential CK-CK# slew rate)
NOTE 2: (ac/dc referenced for 1 V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate)
Table 43. Derating values for DDR3-1600 tDS/tDH – (AC150)
△t , △t derating in [ps] AC/DC based
DS
DH
DQS, DQS# Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
DQ
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
75
50
0
-
50
34
0
-
75
50
0
0
-
50
34
0
-4
-
75
50
0
0
0
-
50
34
0
-4
-10
-
-
58
8
8
8
8
-
-
42
8
-
-
-
16
12
6
-
-
-
-
20
14
8
-
-
-
-
-
-
-
-
-
-
-
-
Slew
Rate
V/ns
-
-
-
16
16
16
16
15
-
4
24
24
24
23
14
-
-
-
-
-
-
-
-2
-8
-
32
32
31
22
7
24
18
8
-
-
-
-
-
-
0
40
39
30
15
34
24
10
-10
-
-
-
-
-
-
-10
-
-2
-16
-
-
-
-
-
-
-
-
-
-6
-26
-
-
-
-
-
-
-
-
-
-
Confidential
-59／83-
Rev. 1.0 May 2016
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
