AS4C128M16D3A-12BIN
Table 26. Latencies and timing parameters relevant for Dynamic ODT
Name and
Description
ODT turn-on
Latency
ODT turn-off
Latency
ODT Latency for
changing from
RTT_Nom to
RTT_WR
ODT Latency for
change from
Definition for all DDR3
speed pin
Abbr.
Defined from
Defined to
Unit
tCK
tCK
registering external
ODT signal high
registering external
ODT signal low
turning
termination on
turning
ODTLon
ODTLoff
ODTLon=WL-2
ODTLoff=WL-2
termination off
change RTT
strength from
RTT_Nom to
RTT_WR
change RTT
strength from
RTT_WR to
RTT_Nom
change RTT
strength from
RTT_WR to
RTT_Nom
ODT registered
low
registering external
write command
ODTLcnw
ODTLcwn4
ODTLcwn8
ODTLcnw=WL-2
tCK
tCK
registering external
write command
ODTLcwn4=4+ODTLoff
ODTLcwn8=6+ODTLoff
RTT_WR to
RTT_Nom (BL=4)
ODT Latency for
change from
registering external
write command
tCK (avg)
RTT_WR to
RTT_Nom (BL=8)
Minimum ODT high time
after ODT assertion
Minimum ODT
high time
after Write (BL=4)
Minimum ODT
high time
ODTH4 registering ODT high
ODTH4=4
ODTH4=4
tCK (avg)
tCK (avg)
registering write with
ODTH4
ODT registered
low
ODT high
registering write with
ODTH8
ODT register low
RTT valid
ODTH8=6
tCK (avg)
tCK (avg)
ODT high
after Write (BL=8)
ODTLcnw
tADC
tADC(min)=0.3tCK(avg)
tADC(max)=0.7tCK(avg)
RTT change skew
ODTLcwn
Note 1: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn)
z Asynchronous ODT Mode
Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen)
in precharge power-down (by MR0 bit A12). Based on the power down mode definitions, this is currently Precharge
power down mode if DLL is disabled during precharge power down by MR0 bit A12.
In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the
external ODT command.
In asynchronous ODT mode, the following timing parameters apply: tAONPD min/max, tAOFPD min/max.
Minimum RTT turn-on time (tAONPD min) is the point in time when the device termination circuit leaves high
impedance state and ODT resistance begins to turn on. Maximum RTT turn on time (tAONPD max) is the point in
time when the ODT resistance is fully on.
tAONPDmin and tAONPDmax are measured from ODT being sampled high.
Minimum RTT turn-off time (tAOFPDmin) is the point in time when the devices termination circuit starts to turn off
the ODT resistance. Maximum ODT turn off time (tAOFPDmax) is the point in time when the on-die termination has
reached high impedance. tAOFPDmin and tAOFPDmax are measured from ODT being sample low.
Table 27. ODT timing parameters for Power Down (with DLL frozen) entry and exit
Description
Min
Max
ODT to RTT
turn-on delay
min{ ODTLon * tCK + tAONmin; tAONPDmin } max{ ODTLon * tCK + tAONmax; tAONPDmax }
min{ (WL - 2) * tCK + tAONmin; tAONPDmin } max{ (WL - 2) * tCK + tAONmax; tAONPFmax }
ODT to RTT
turn-off delay
min{ ODTLoff * tCK + tAOFmin; tAOFPDmin } max{ ODTLoff * tCK + tAOFmax; tAOFPDmax }
min{ (WL - 2) * tCK + tAOFmin; tAOFPDmin }
max{ (WL - 2) * tCK + tAOFmax; tAOFPDmax }
tANPD
WL - 1
Confidential
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Rev. 1.0 May 2016
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
