AS4C128M16D3A-12BIN
z Self-Refresh Operation
The Self-Refresh command can be used to retain data in the DDR3 SDRAM, even if the reset of the system is
powered down. When in the Self-Refresh mode, the DDR3 SDRAM retains data without external clocking. The
DDR3 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Entry (SRE)
Command is defined by having CS#, RAS#, CAS#, and CKE held low with WE# high at the rising edge of the clock.
Before issuing the Self-Refreshing-Entry command, the DDR3 SDRAM must be idle with all bank precharge state
with tRP satisfied. Also, on-die termination must be turned off before issuing Self-Refresh-Entry command, by either
registering ODT pin low “ODTL + 0.5tCK” prior to the Self-Refresh Entry command or using MRS to MR1 command.
Once the Self-Refresh Entry command is registered, CKE must be held low to keep the device in Self-Refresh
mode. During normal operation (DLL on), MR1 (A0=0), the DLL is automatically disabled upon entering Self-
Refresh and is automatically enabled (including a DLL-RESET) upon exiting Self-Refresh.
When the DDR3 SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE and
RESET#, are “don’t care”. For proper Self-Refresh operation, all power supply and reference pins (VDD, VDDQ,
VSS, VSSQ, VRefCA, and VRefDQ) must be at valid levels. The DRAM initiates a minimum of one Refresh
command internally within tCKE period once it enters Self-Refresh mode.
The clock is internally disabled during Self-Refresh operation to save power. The minimum time that the DDR3
SDRAM must remain in Self-Refresh mode is tCKE. The user may change the external clock frequency or halt the
external clock tCKSRE after Self-Refresh entry is registered; however, the clock must be restarted and stable
tCKSRX before the device can exit Self-Refresh mode.
The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE
going back HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or
Deselect on command bus) is registered, a delay of at least tXS must be satisfied before a valid command not
requiring a locked DLL can be issued to the device to allow for any internal refresh in progress.
Before a command which requires a locked DLL can be applied, a delay of at least tXSDLL and applicable ZQCAL
function requirements [TBD] must be satisfied.
Before a command that requires a locked DLL can be applied, a delay of at least tXSDLL must be satisfied.
Depending on the system environment and the amount of time spent in Self-Refresh, ZQ calibration commands
may be required to compensate for the voltage and temperature drift as described in “ZQ Calibration Commands”.
To issue ZQ calibration commands, applicable timing requirements must be satisfied.
CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self-Refresh
re-entry. Upon exit from Self-Refresh, the DDR3 SDRAM can be put back into Self-Refresh mode after waiting at
least tXS period and issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be
registered on each positive clock edge during the Self-Refresh exit interval tXS. ODT must be turned off during
tXSDLL.
The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed when
CKE is raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3 SDRAM requires a minimum
of one extra refresh command before it is put back into Self-Refresh mode.
Confidential
-45／83-
Rev. 1.0 May 2016
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
