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AS4C128M16D3A-12BIN 参数 Datasheet PDF下载

AS4C128M16D3A-12BIN图片预览
型号: AS4C128M16D3A-12BIN
PDF下载: 下载PDF文件 查看货源
内容描述: [AS4C128M16D3A-12BIN - 96 ball FBGA PACKAGE]
分类和应用:
文件页数/大小: 83 页 / 2180 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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AS4C128M16D3A-12BIN  
128M x 16 bit DDR3 Synchronous DRAM (SDRAM)  
Features  
Overview  
JEDEC Standard Compliant  
The 2Gb Double-Data-Rate-3 DRAMs is double data  
rate architecture to achieve high-speed operation. It is  
internally configured as an eight bank DRAM.  
Power supplies: VDD & VDDQ = +1.5V ± 0.075V  
Operating temperature: -40~95 C (TC)  
°
Supports JEDEC clock jitter specification  
Fully synchronous operation  
Fast clock rate: 800MHz  
Differential Clock, CK & CK#  
Bidirectional differential data strobe  
- DQS & DQS#  
8 internal banks for concurrent operation  
8n-bit prefetch architecture  
Pipelined internal architecture  
Precharge & active power down  
Programmable Mode & Extended Mode registers  
Additive Latency (AL): 0, CL-1, CL-2  
Programmable Burst lengths: 4, 8  
Burst type: Sequential / Interleave  
The 2Gb chip is organized as 16Mbit x 16 I/Os x 8  
bank devices. These synchronous devices achieve  
high speed double-data-rate transfer rates of up to  
1866 Mb/sec/pin for general applications.  
The chip is designed to comply with all key DDR3  
DRAM key features and all of the control and address  
inputs are synchronized with a pair of externally  
supplied differential clocks. Inputs are latched at the  
cross point of differential clocks (CK rising and CK#  
falling). All I/Os are synchronized with differential DQS  
pair in a source synchronous fashion.  
These devices operate with a single 1.5V ± 0.075V  
power supply and are available in BGA packages.  
Output Driver Impedance Control  
8192 refresh cycles / 64ms  
- Average refresh period  
7.8µs @ -40°C TC+85°C  
3.9µs @ +85°C TC+95°C  
Write Leveling  
ZQ Calibration  
Dynamic ODT (Rtt_Nom & Rtt_WR)  
RoHS compliant  
Auto Refresh and Self Refresh  
96-ball 8 x 13 x 1.0mm FBGA package  
- Pb and Halogen Free  
Table 1. Ordering Information  
Org  
Temperature  
Max Clock (MHz)  
Product part No  
Package  
800  
128M x 16  
AS4C128M16D3A-12BIN  
96-ball FBGA  
Industrial -40°C to 95°C  
Table 2. Speed Grade Information  
Speed Grade  
Clock Frequency CAS Latency  
tRCD  
tRP  
(ns)  
(ns)  
13.75  
13.75  
800 MHz  
11  
DDR3-1600  
Confidential  
-283-  
Rev. 1.0 May 2016