AS4C128M16D2
Basic Functionality
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst
length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then
followed by a Read or Write command. The address bits registered coincident with the active command are used to select the
bank and row to be accessed (BA0, BA1 select the bank; A0-A13 select the row). The address bits registered coincident with the
Read or Write command are used to select the starting column location for the burst access and to determine if the auto
precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device
initialization, register definition, command descriptions and device operation.
Power up and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may
result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT*1 at a low state (all other inputs may be
undefined.)
- VDD, VDDL and VDDQ are driven from a single power converter output, AND
- VTT is limited to 0.95V max, AND
- Vref tracks VDDQ/2.
or
- Apply VDD before or at the same time as VDDL.
- Apply VDDL before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref. at
least one of these two sets of conditions must be met.
2. Start clock and maintain stable condition.
3. For the minimum of 200us after stable power and clock (CK, CK), then apply NOP or deselect & take CKE high.
4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period.
5. Issue EMRS(2) command. (To issue EMRS(2) command, provide “Low” to BA0, “High” to BA1.)
6. Issue EMRS(3) command. (To issue EMRS(3) command, provide “High” to BA0 and BA1.)
7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to
BA1 and A12.)
8. Issue a Mode Register Set command for “DLL reset”.
(To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1)
9. Issue precharge all command.
10. Issue 2 or more auto-refresh commands.
11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating
parameters without resetting the DLL.
12. At least 200 clocks after step 8, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Exit
command (A9=A8=A7=0) must be issued with other operating parameters of EMRS.
13. The DDR2 SDRAM is now ready for normal operation.
Confidential
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Version 2.0 – Oct/2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
