$XJXVW
$GYDQFHG ,QIRUPDWLRQ
$6 /9
9 0 î 0 î &026 )ODVK ((3520
)HDWXUHV
• Organization: 2M×8 / 1M×16
• Sector architecture
- One 16K; two 8K; one 32K; and thirty-one 64K byte sectors
- One 8K; two 4K; one 16K; and thirty-one 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 2.7-3.6V power supply for read/write operations
• Sector protection
• High speed 70/80/90/120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
• Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
• Hardware RESET pin
- Resets internal state machine to read mode
• Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO (availability TBD)
• CFI (Common Flash Interface) compliant
• Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
- RY/BY output
• Erase suspend/resume
- Supports reading data from or programming data to a
sector not being erased
• Low V
CC
write lock-out below 1.5V
• 10 year data retention at 150C
• 100,000 write/erase cycle endurance
/RJLF EORFN GLDJUDP
RY/BY
V
CC
V
SS
RESET
Program/erase
control
Command
register
CE
OE
Program voltage
generator
Chip enable
Output enable
Logic
STB
Data latch
Sector protect/
erase voltage
switches
Erase voltage
generator
DQ0–DQ15 (A-1)
3LQ DUUDQJHPHQW
48-pin TSOP
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
44-pin SO
Reset
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WE
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
Input/output
buffers
WE
BYTE
$6 /9
V
CC
detector
Timer
Address latch
STB
Y decoder
Y gating
X decoder
Cell matrix
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
V
SS
CE
A0
A0–A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
6HOHFWLRQ JXLGH
29LV160-70
Maximum access time
Maximum chip enable access time
Maximum output enable access time
t
AA
t
CE
t
OE
70
70
30
29LV160-80
80
80
30
29LV160-90
90
90
35
29LV160-120
120
120
50
Unit
ns
ns
ns
8/30/01; V.0.9.5
$OOLDQFH 6HPLFRQGXFWRU
P. 1 of 29
&RS\ULJKW $OOLDQFH 6HPLFRQGXFWRU $OO ULJKWV UHVHUYHG
$6 /9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
