AS29F400
Preliminary information
®
Command definitions
Item
Description
Initiate read or reset operations by writing the Read/Reset command sequence into the command
register. This allows the microprocessor to retrieve data from the memory. Device remains in read
mode until command register contents are altered.
Reset/Read
Device automatically powers up in read/reset state. This feature allows only reads, therefore
ensuring no spurious memory content alterations during power up.
AS29F400 provides manufacturer and device codes in two ways. External PROM programmers
typically access the device codes by driving +12V on A9. AS29F400 also contains an ID Read
command to read the device code with only +5V, since multiplexing +12V on address lines is
generally undesirable.
Initiate device ID read by writing the ID Read command sequence into the command register.
Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command
sequence with a read sequence from address XXX01h to return device code.
ID Read
To verify write protect status on sectors, read address XXX02h. Sector addresses A17–A12 produce
a 1 on DQ0 for protected sector and a 0 for unprotected sector.
Exit from ID read mode with Read/Reset command sequence.
Holding RESET low for 500 ns resets the device, terminating any operation in progress; data
handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driven
low. RY/BY remains low until the RESET operation is completed. After RESET is set high, there is a
delay of 1.5 µs for the device to permit read operations.
Hardware Reset
Programming the AS29F400 is a four bus cycle operation performed on a byte-by-byte or word-
by-word basis. Two unlock write cycles precede the Program Setup command and program data
write cycle. Upon execution of the program command, no additional CPU controls or timings are
necessary. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched
on the rising edge of CE or WE, whichever is first. The AS29F400’s automated on-chip program
algorithm provides adequate internally-generated programming pulses and verifies the
programmed cell margin.
Check programming status by sampling data on the DATA polling (DQ7), toggle bit (DQ6), or
RY/BY pin. The AS29F400 returns the equivalent data that was written to it (as opposed to
complemented data), to complete the programming operation.
Byte/word
Programming
The AS29F400 ignores commands written during programming. A hardware reset occurring
during programming may corrupt the data at the programmed location.
AS29F400 allows programming in any sequence, across any sector boundary. Changing data from
0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1
(exceeded programming time limits) or success according to DATA polling; reading this data after
a read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high,
and DQ6 continues to toggle. In this state, a Reset command returns the device to read mode.
Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional
unlock write cycles; and finally the Chip Erase command.
Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip
erase algorithm is invoked with the Chip Erase command sequence, AS29F400 automatically
programs and verifies the entire memory array for an all-zero pattern prior to erase. The AS29F200
returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding
time limit.
Chip Erase
6
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
