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20 ns 20 ns 20 ns
+0.8V
-0.5V
-2.0V
0D[LPXP#SRVLWLYH#RYHUVKRRW#ZDYHIRUP
V +2.0V
CC
V +0.5V
CC
+2.0V
20 ns 20 ns 20 ns
$&#SDUDPHWHUV=#UHDG#F\FOH
-55
-70
-90
-120
JEDEC Std
Symbol Symbol
Parameter
Min Max Min Max Min Max Min Max Unit
tAVAV tRC
Read cycle time
55
-
-
70
-
-
90
-
-
120
-
ns
ns
ns
ns
ns
ns
tAVQV tACC
tELQV tCE
tGLQV tOE
tEHQZ tDF
tGHQZ tDF
Address to output delay
Chip enable to output
Output enable to output
Chip enable to output High Z
Output enable to output High Z
55
55
25
15
15
70
70
30
20
20
90
90
35
20
20
-
-
-
-
-
120
120
50
-
-
-
-
-
-
-
-
-
30
-
-
-
30
Output hold time from addresses,
first occurrence of CE or OE
tAXQX tOH
0
-
0
-
0
-
0
-
ns
tELFL/ ELFH CE to BYTE transition low/ high
-
-
5
1.5
55
-
-
-
5
1.5
70
-
-
-
5
1.5
90
-
-
-
5
1.5
120
-
ns
µs
ns
ns
tPHQV tPWH
tBDEL
tFLQZ
RESET high to output delay
BYTE switching to valid data
BYTE low to DQ8–DQ15 tri-state
-
-
-
-
30
30
35
50
5HDG#ZDYHIRUP
tRC
Addresses stable
tACC
Addresses
CE
tDF
tOE
OE
tOEH
WE
tOH
Output valid
tCE
High Z
High Z
Outputs
BYTE
tELFL/ ELFH
tBDEL
tPWH
RESET
45
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