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-55
-70
-90
-120
-150
JEDEC
Std
Symbol Symbol Parameter
Min Max Min Max Min Max Min Max Min Max Unit
tAVAV
tRC
tACC
tCE
tOE
tDF
tDF
Read cycle time
55
-
-
70
-
-
90
-
-
120
-
150
-
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
Address to outputdelay
Chip enable to output
55
55
25
15
15
70
70
30
20
20
90
90
35
20
20
-
-
-
-
-
120
120
50
-
-
-
-
-
150
150
55
-
-
-
Output enable to output
Chip enable to output High Z
Output enable to output High Z
-
-
-
-
-
-
30
35
-
-
-
30
35
Output hold time from addresses,
CE or OE, whichever occurs first
tAXQX
tOH
0
-
0
-
0
-
0
-
0
-
ns
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Rising input
Falling input
Undefined / don’t care
5HDG#ZDYHIRUP
tRC
Addresses stable
tACC
Addresses
CE
tDF
tOE
OE
WE
tOH
tCE
High Z
High Z
Outputs
Output valid
45
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