$65<)343
®
$&#SDUDPHWHUV#³#UHDG#F\FOH
+9&&# #813“3189/#966# #39/#7D# #3ƒ&#WR#.:3ƒ&,
-120 -150
JEDEC
symbol
Std symbol Parameter
Min
Max
-
Min
Max
-
Unit
ns
tAVAV
tRC
tACC
tCE
tOE
tDF
tDF
Read cycle time
120
150
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
Address to output delay
-
-
-
-
-
120
120
50
-
-
-
-
-
150
150
50
ns
Chip enable to output
ns
Output enable to output
Chip enable to output High Z
Output enable to output High Z
ns
30
30
ns
30
30
ns
Output hold time from addresses, first
occurrence of CE or OE
tAXQX
tOH
0
-
0
-
ns
$&#SDUDPHWHUV#³#ZULWH#F\FOH
+9&&# #813“3189/#966# #39/#7D# #3ƒ&#WR#.:3ƒ&,
-120 -150
JEDEC
symbol
Std symbol Parameter
tWC Write cycle time
tAS
tAH
tDS
tDH
tOES
Min
120
0
Max
Min
150
0
Max
Unit
ns
tAVAV
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tAVWL
tWLAX
tDVWH
tWHDX
Address setup time
Address hold time
ns
50
50
0
50
50
0
ns
Data setup time
ns
Data hold time
ns
Output enable setup time
Output enable hold time: Read
0
0
ns
0
0
ns
tOEH
Output enable hold time:
Toggle and DATA polling
10
-
10
-
ns
tGHWL
tELWL
tGHWL
tCS
Read recover time before write
CE setup time
0
0
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
µs
µs
µs
tWHEH
tWLWH
tWHWL
tWHWH1
tWHWH2
tCH
CE hold time
0
0
tWP
Write pulse width
Write pulse width high
Programming pulse time
Erase pulse time
80
20
250
1000
2
80
20
250
1000
2
tWPH
tWHWH1
tWHWH2
tVCS
VCC setup time
9
$//,$1&(#6(0,&21'8&725
','#4407333:0$1#72:233