#
®
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0RGH#WDEOH
Mode
Read
Output disable
Standby
Mfr. code
Device code
Write command
†
Key:
CE
L
L
H
L
L
L
OE
L
H
H
L
L
H
WE
H
H
H
H
H
L
A0
A0
X
X
L
H
A0
A9
A9
X
X
Vh
Vh
A9
DQ
D
OUT
High Z
High Z
52h
CODE (03h,04h,06h)
D
IN
L =Low (<VIL); H = High (>VIH); Vh = 11.5–12.5V; X =Don’t care
Read mode:
Selected with CE and OE low, WE high. Data is valid tAA after addresses are stable, tCE after CE is low and tOE after OE is low.
Output disable:
Part remains powered up; but outputs disabled with OE pulled high.
Standby:
Part is powered down, and ICC reduced to 1.5 mA for TTL input levels (<1.0 mA for CMOS input levels).
Mfr. (manufacturer) code, Device code:
Selected by A9 = 11.5–12.5V. When CE and OE are pulled low the outputs are enabled and a data byte is read out.
When A0 is pulled low the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high DOUT = 03h,04h, 06h, the
Alliance device codes for the AS29F010.
Write command:
Selected by CE and WE pulled low, OE pulled high. Initiates command mode in the WSM and latches addresses and data into the chip. Once
a write command starts, the WSM stays in command mode until the command is completed or it times out. Addresses are latched on the falling edge of WE
and CE, whichever occurs later; data is latched on the rising edge o WE and CE, whichever occurs first. The WE signal is filtered to prevent spurious events
from being detected as write commands.
&RPPDQG#IRUPDW
All commands require four bus write cycles to execute. After four write cycles the command is executed until terminated by the i nternal
timer. For verify commands a read operation after Write
[4]
in a write command bus cycle reads out the data from thearray. For manufacturer
and device code commands the ID code is read out. For other operations a read operation reads out a status byte on the outputs.
Address in
Bus write
[1]
Bus write
[2]
Bus write
[3]
Bus write
[4]
Bus read
5555h
2AAAh
5555h
Address in
Address in
Data in
AAh
55h
Command code
Data in
D
OUT
Command timeout:
For each operation the address and data are latched at
bus Write
[4]
and held until the operation completes and times-out. After
time-out the WSM returns the AS29F010 to normal mode. Each individual
operation requires the 4-cycle write command sequence to execute. The
AS29F010 does not remain in command mode after time-out. When a
command times-out only the error flag is not reset.
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Errors a
nd timeout:
Any of the following conditions sets the error flag.
• Any write command which does not match the sequence above for Write
{1]
. Write
{2]
, and Write
[3]
.
• Any write cycle that follows more than 150 µs after the previous write cycle.
• The command Data
[3]
in Write
[3]
has more than one bit set high. This indicates conflicting commands.
• V
CC
drops below V
LKO
during command execution.
Once the error flag is set, the AS29F010 times out and returns to normal Readmode. The error flag remains until it is cleared by a reset
command. The error flag can be read by executing a status command and reading the status byte.
&RPPDQG#FRGHV#DQG#WLPH#RXW
The Command Code table displays the bus cycles required for each command mode. Read delay is the minimum delay after Write
[4]
during
a write command bus cycle before a valid read may be executed. Timeout indicates the maximum delay before the WSM returns the
AS29F010 to normal mode. Erase has a longer timeout than the other modes. Status byte can be read almost immediately after a Write
[4]
, but
the verify commands require a 25 µs delay to read valid data.
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6
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
