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Status
Auto programming (byte/word)
Program/erase in auto erase
Read erasing sector
In progress
Erase
suspend
mode
Read non-erasing
sector
Program in erase
suspend
DQ7
DQ7
0
1
Data
DQ7
DQ7
0
DQ7
DQ6
Toggle
Toggle
No toggle
Data
Toggle
Toggle
Toggle
Toggle
DQ5
0
0
0
Data
0
1
1
1
DQ3
0
1
0
Data
0
NA
1
NA
DQ2
No toggle
Toggle
†
Toggle
Data
Toggle
†
No toggle
Toggle
‡
RY/BY
0
0
1
1
0
1
1
Auto programming (byte/word)
Exceeded time limits
†
‡
Program/erase in auto erase
Program in erase suspend
No toggle
‡
1
Toggles with OE or CE only for erasing or erase suspended sector addresses.
Toggles only if DQ5 = 1 and address applied is within sector that exceeded timing limits.
DQ8–DQ15 = Don’t care in ×16 mode.
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Item
Description
Initiate read or reset operations by writing the Read/Reset command sequence into the command
register. This allows the microprocessor to retrieve data from the memory. Device remains in read
mode until command register contents are altered.
Device automatically powers up in read/reset state. This feature allows only reads, therefore
ensuring no spurious memory content alterations during power up.
AS29F002 provides manufacturer and device codes in two ways. External PROM programmers
typically access the device codes by driving +12V on A9. AS29F002 also contains an ID read
command to read the device code with only +5V, since multiplexing +12V on address lines is
generally undesirable.
Reset/Read
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ID Read
Initiate device ID read by writing the ID Read command sequence into the command register.
Follow with a read sequence from address XX00h to return MFG code. Follow ID read command
sequence with a read sequence from address XX01h to return device code.
To verify write protect status on sectors, read address XX02h. Sector addresses A17–A13 produce
a 1 on DQ0 for protected sector and a 0 for unprotected sector.
Exit from ID read mode with Read/Reset command sequence.
Holding RESET low for 500 ns resets the device, terminating any operation in progress; data
handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is
driven low. After RESET is set high, there is a delay of 1.5 µs for the device to permit read
operations.
Hardware reset
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ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
