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• Organization:
256K×8
• Sector architecture
- One 16K; two 8K; one 32K; and three 64K byte sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 5.0±0.5V power supply for read/write operations
• Sector protection
• High speed 55/70/90/120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
• Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified sec-
tors
• 10,000 write/erase cycle endurance
• Hardware RESET pin
- Resets internal state machine to read mode
• Low power consumption
- 40 mA maximum read current
- 60 mA maximum program current
- 2 mA maximum standby current
- 10 µA standby current (RESET = 0)
• JEDEC standard software, packages and pinouts
- 40-pin TSOP
- 32-pin PLCC
- 32-pin TSOP
- 32-pin PDIP
• Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
• Erase suspend/resume
- Supports reading data from a sector not being erased
• Low V
CC
write lock-out below 2.8V
3LQDUUDQJHPHQW
40-pin TSOP
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A11
A9
A8
A13
A14
A17
WE
V
CC
RESET
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
32
31
30
29
V
CC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
WE
A17
A14
A13
A8
A9
A11
OE
DQ1
DQ2
V
SS
DQ3
DQ4
DQ5
DQ6
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
32-pin TSOP
32-pin PDIP
32-pin PLCC
A12
A15
A16
RESET
V
CC
WE
A17
AS29F002
5
6
7
8
9
10
11
12
13
14
15
16
28
27
26
25
24
23
22
21
20
19
18
17
AS29F002
AS29F002
)/$6+
AS29F002
6HOHFWLRQJXLGH
AS29F002-55 AS29F002-70 AS29F002-90 AS29F002-120
Maximum access time
Maximum chip enable access time
Maximum output enable access time
t
AA
t
CE
t
OE
55
55
25
70
70
30
90
90
35
120
120
50
Unit
ns
ns
ns
',' $
',' $
$//,$1&(6(0,&21'8&725
14
15
16
17
18
19
20
A17
V
SS
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
CC
NC
DQ3
DQ2
DQ1
DQ0
OE
V
SS
CE
A0
Copyright ©1998 Alliance Semiconductor. All rights reserved.
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
